The present invention relates to the deposition of dielectric layers during wafer processing, and more specifically, to a method and apparatus for depositing a silicon oxide film having reduced bulk oxide traps within the film. Silicon oxide films deposited according to the present invention are particularly useful as an initial lining layer in composite layer premetal dielectric films but are also useful in other applications.
Chemical vapor deposition (CVD) of silicon oxide films is one of the primary steps in the fabrication of many modern semiconductor devices. Such silicon oxide films are widely used as insulating layers between adjacent metal layers, between a silicon substrate and an initial metal layer, between the silicon substrate and a polysilicon or metal gate structure and as oxide sidewalls among many other uses. One particular use for a silicon oxide film is as an initial layer in a composite layer film that separates the polysilicon gate/interconnect layer and the first metal layer of MOS transistors. Such separation layers are referred to as premetal dielectric (PMD) layers because they are typically deposited before any of the metal layers in a multilevel metal structure.
An example of a PMD layer is shown in FIG. 1, which is a simplified cross-sectional view of a partially completed prior art integrated circuit 10. In FIG. 1, a transistor 14 is fabricated on the surface of a silicon substrate 12. Transistor 14 includes a source region 16, a drain region 18 and a gate region 20. A metal contact 22 connects an overlying metal line 24 to drain region 18, while a PMD layer 26 separates metal line 24 from polysilicon gate 20 and silicon substrate 12 (except for at contact 22). Also shown in FIG. 1 is a first layer 28 of a composite layer intermetal dielectric film that separates metal layer 24 from overlying metal layers (not shown), and field oxide (FOX) regions 30, which separate and electrically isolate transistor 14 from other devices fabricated on substrate 12.
As shown in FIG. 1, PMD layer 26 is a composite layer film including a first silicon oxide layer 32 and a second borophosphosilicate glass (BPSG) layer 34. Silicon oxide layer 32 is deposited over a surface that contains raised or stepped structures (e.g., gate 20 and FOX regions 30). As initially deposited, layer 32 generally conforms to the topography of the underlying surface and is typically planarized or flattened to achieve the shape shown in FIG. 1 before overlying layer 34 is deposited. One way to planarize silicon oxide layer 32 is to deposit a photoresist layer (a nonconformal layer) over the film and etchback the photoresist/silicon oxide combination.
After layer 32 is planarized, BPSG layer 34 is then deposited over layer 32. BPSG layer 34 may then be further planarized or flattened before an overlying metal layer is deposited. Several different techniques may be used to planarize BPSG layer 32. For example, a standard reflow process, in which the BPSG film is heated to a temperature at which it flows, may be employed to planarize the film. Alternatively, a chemical mechanical polishing (CMP) or etching technique may be used. As an example of this method in fabrication devices having minimum feature sizes of 0.5 xcexcm, silicon oxide layer 34 may be 9000 xc3x85 as initially deposited, but then be etched back to be only 3000 xc3x85 thick, while BPSG layer 34 may be 5000 xc3x85 thick.
In depositing such a PMD layer, it is important that the physical and electrical properties of the layer be within specified ranges as determined by the semiconductor manufacturer. Such importance cannot be overstated because these properties directly effect the electrical characteristics and operation of the transistors and other structures formed on the substrate, which in turn directly effect the operation of the semiconductor device or integrated circuit. Two such electrical characteristics of fabricated transistors and diodes include the breakdown voltage and leakage current of the structures. If these characteristics are not within the manufacturer""s specifications, the integrated circuit containing the transistors and/or diodes may be defective.
One known method of depositing silicon oxide layer 32 described above includes flowing a process gas containing tetraethylorthosilicate (TEOS) and O2 into a P5000 lamp-heated CVD deposition chamber manufactured by Applied Materials, the assignee of the present invention. In this method, the process gas is introduced into the CVD chamber through an anodized aluminum faceplate, and a plasma is formed between the faceplate and a susceptor upon which a substrate rests by applying RF energy to the faceplate. As is usual in deposition processes of this type, in addition to depositing a silicon oxide film over the substrate, the process gas causes unwanted deposition on areas such as the interior walls of the processing chamber. Unless removed, this unwanted deposition is a source of contaminate particles that may interfere with subsequent processing steps and adversely effect wafer yield.
To avoid such problems in this known method, the inside surface of the chamber is regularly cleaned after processing n wafers (where n is generally between 1-8 depending on the thickness of the deposited film) to remove the unwanted deposition material from the chamber walls. To perform such a cleaning operation, a fluorine-containing gas, such as nitrogen trifluorine (NF3), is used to remove (etch) the deposited material from the chamber walls and other areas. The etchant gas is introduced into the chamber and a plasma is formed so that the etchant gas reacts with and removes the deposited material from the chamber walls. Such a process (deposition step and clean step combination) has been successfully used to deposit silicon oxide layers 32 of PMD layers such as layer 26 in the fabrication of many different types of integrated circuits.
In the semiconductor fabrication field, new technology is constantly being developed to allow for the deposition of silicon oxide and other films having improved properties. One example of such improved technology is the development of the DxZ chamber by Applied Materials, the assignee of the present invention. The DxZ chamber, which is further described in U.S. Pat. No. 5,558,717, allows for improved film deposition for some processes as compared to prior art deposition chambers. Sometimes, processes that were successfully implemented on older technology equipment, however, are not ideally suited for such newer equipment. For example, when the process described above to deposit silicon oxide layer 32 was attempted on a DxZ chamber, an increased level of bulk oxide traps were created within the deposited silicon oxide film. In some instances, the increased number of such bulk oxide traps was sufficient to lower the breakdown voltage and increase the current leakage of transistor and diode devices fabricated with such films to unacceptable levels.
Accordingly, new deposition techniques are continuously being sought to better use newly developed technology.
The present invention provides an improved method for depositing silicon oxide dielectric layers having reduced oxide trapped charges within the bulk layer of the deposited film. Bulk oxide traps are reduced by adding a chemical source to the deposition process to create interactions with the silicon oxide film being deposited that reduce the bulk oxide traps within the film. The chemical source selected is one that promotes such bulk oxide trap reducing interactions. Examples of such a chemical source include fluorine-containing sources such as NF3, C2F6, CF4 and F2 among other chemical sources.
One embodiment of the method of the present invention includes the steps of distributing a fluorine source to a processing chamber at a selected rate with the rate being chosen to incorporate between about 1xc3x971019 atoms/cm3 and 3xc3x971021 atoms/cm3 of fluorine into the film; flowing a process gas including a silicon source, an oxygen source and the fluorine source into the processing chamber; and maintaining a deposition zone within the chamber at processing conditions suitable to deposit, over a substrate disposed in the chamber, a silicon oxide film having the desired level of fluorine incorporated therein. In a preferred version of this embodiment, the desired level of fluorine incorporated into the film is between about 5xc3x971019 atoms/cm3 and 1xc3x971021 atoms/cm3. In an even more preferred embodiment, the fluorine level is between 1xc3x971020 atoms/cm3 and 1xc3x971021 atoms/cm3.
In another embodiment of the present invention, a method is disclosed for fabricating an integrated circuit. In this embodiment, transistors are formed upon the surface of a substrate. Afterwards, but prior to depositing any metal layers over the substrate, a first, silicon oxide layer of a composite dielectric layer is deposited over the substrate from a process gas that includes a silicon source, an oxygen source and a fluorine source. The amount of fluorine source in the process gas is selected to deposit a film having between 1xc3x971019 and 3xc3x971021 fluorine atoms/cm3 within the film. Next, a second layer of the composite layer dielectric layer is deposited over the first layer. In a preferred version of this embodiment, the second layer of the composite layer is a BPSG film and the fluorine content of the first layer is between about 5xc3x971019 atoms/cm3 and 1xc3x971021 atoms/cm3. In an even more preferred embodiment the fluorine content of the first layer is between 1xc3x971020 atoms/cm3 and 1xc3x971021 atoms/cm3.